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256-position one-time programmable dual-channel i 2 c digital potentiometers ad5172/ad5173 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 2-channel, 2 56- positi on device s otp (one-ti m e p r ogramma ble ) set-and-forget resi stance setti ng, low co st alt e rnative to ee me m unlimite d a d justments prior to otp activ a tion otp over writ e a l lows dyna mic a d justm e nts wit h user -defin ed pr eset end-t o -en d re si stance: 2. 5 k ? , 10 k ? , 50 k ? , 1 00 k ? compact m s op-10 (3 mm 4.9 mm) packag e fast settlin g tim e : t s = 5 s typ in pow e r- up full r ead/writ e of wip e r re giste r power-on pr ese t to mi dscale extra pack age a ddr es s deco de pins a d 0 and a d 1 (ad 517 3) single su pply: 2 . 7 v t o 5. 5 v low temp eratu r e coefficient: 3 5 ppm/c low po wer: i dd = 6 a m a x wide oper ating temperat ure: C4 0c to +125 c evaluati on b o ar d an d softwar e are avai lable softwar e re plac es c in factory program m ing a pplicati o ns applic ati o ns system s c a libra t ion electronic s l e vel setting mechanical tri mmers? repl ace m ent in n e w de signs perman ent fact ory pc b setting transduc er a d ju stment of pre s sure, t e mper atur e, po sition , chemical, and o p tical sensors rf ampl ifier bia sing automotiv e ele c tronics a d just ment gain c o ntrol an d offset a d just ment general overview the ad5172 /ad5173 a r e d u al-c ha nne l , 256 -p o s i t io n, on e-tim e p r o g ra mma b l e (otp) d i g i t a l p o ten t iometers 1 th a t e m p l o y fu s e l i n k te c h no l o g y to a c h i e v e me mor y re t e n t i o n of re s i s t a n c e s e tt i n g . o t p is a cos t -ef f ec ti v e al t e r n a t iv e t o eemem f o r user s wh o do not ne e d to pro g r a m t h e d i g i t a l p o te n t i o me t e r s e tt i n g i n me mor y m o r e th a n o n ce . t h i s de v i ce perf o r m s th e sa m e e l ectr o n i c ad j u st m e n t f u nc t i o n as m e chanica l p o t e n t iomet e rs o r va r i ab le r e sis t o r s wi t h e n han c e d r e s o l u t i o n , s o lid-sta t e r e l i a b ili t y , and s u p e r i o r lo w t e m p era t ur e co ef f i cien t p e r f o r ma n c e. the ad5172 /ad5173 a r e p r ogra mm e d usin g a 2-wir e , i 2 c- co m p a t i b le dig i tal in t e r f ac e . u n limi t e d ad j u s t men t s a r e al lo we d b e f o re p e r m a n e n t l y s e tt i n g t h e re s i st anc e v a lu e. d u r i ng o t p ac t i va t i o n , a p e r m a n e n t b l o w -f u s e co mmand f r e e z es t h e w i p e r p o si t i o n (a na lo go us t o placin g ep o x y o n a m e cha n ica l t r im m e r). func tio n a l block di agrams a1 v dd g nd sda scl w1 rdac register 1 serial input register 04103-0-001 b1 a2 w2 rdac register 2 b2 fuse links 12 / 8 f i g u re 1. a d 51 72 v dd g nd sda scl ad0 ad1 w1 rdac register 1 address decode serial input register b1 w2 rdac register 2 b2 fuse links 12 / 8 04103-0-002 f i g u re 2. a d 51 73 u n like tradi t io nal o t p dig i tal p o t e n t iomet e rs, t h e ad5172/ ad5173 ha ve a uniq ue tem p o r a r y o t p o v er wr i t e f e a t ur e tha t all o w s f o r n e w ad j u s t m e n t s ev en a f t e r a fuse h a s been b l o w n . h o w e v e r , t h e otp s e t t in g is r e st o r e d d u r i n g subs e q ue n t p o w e r - u p co n d i ti o n s. t h i s f e a t ur e allo w s use r s t o tr ea t th e s e di gi t a l p o te n t i o me te rs a s vol a t i l e p o te n t i o me te rs w i t h a pro g r a mmabl e p r es et. f o r a p p l ica t ion s tha t p r og ra m t h e ad5172/ad5173 a t t h e f a c t or y , a n a l o g d e v i c e s of f e r s d e v i c e pro g r a m m i ng s o f t w a re r u nnin g o n w i n d o w s? n t ?, 20 00, a nd xp? o p e r a t in g sy ste m s. t h i s s o f t w a re e f f e c t ively re p l a c e s an y e x te r n a l i 2 c co n t r o l l ers, t h us enhan c i n g t h e t i m e -t o-ma rk et o f t h e us er s sys t em s. 1 the te rms d i gital po te ntio m e t e r, vr, and rda c are us ed inte rchange a bl y.
ad5172/ad5173 rev. b | page 2 of 24 table of contents electrical characteristics2.5 k? version ................................... 3 electrical characteristics10 k?, 50 k?, 100 k? versions ....... 4 timing characteristics2.5 k?, 10 k?, 50 k?, 100 k? versions ............................................................................................................. 5 absolute maximum ratings ............................................................ 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circ u its ..................................................................................... 12 theory of operation ...................................................................... 13 one-time programming (otp) .............................................. 13 programming the variable resistor and voltage ................... 13 programming the potentiometer divider ............................... 14 esd protection ........................................................................... 15 terminal voltage operating range ......................................... 15 power-up sequence ................................................................... 15 power supply considerations ................................................... 15 layout considerations ............................................................... 16 evaluation software/hardware ..................................................... 17 software programming ............................................................. 17 i 2 c interface .................................................................................... 19 i 2 c-compatible 2-wire serial bus ........................................... 21 outline dimensions ....................................................................... 23 ordering guide ............................................................................... 24 revision history 11/04changed from rev. a to rev. b updated format.................................................................. universal changes to specifications .................................................................3 changes to one-time programming (otp) section.................13 changes to power supply considerations section......................15 changes to figure 44 and figure 45..............................................15 changes to figure 46 and figure 47..............................................16 changes to ordering guide ...........................................................24 11/03changed from rev. 0 to rev. a changes to electrical characteristics2.5 k?................................3
ad5172/ad5173 rev. b | page 3 of 24 electrical characteristics2.5 k? version v dd = 5 v 10% or 3 v 10%; v a = +v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C6 0.75 +6 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +55 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c rwb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C10 C2.5 0 lsb zero-scale error v wzse code = 0x00 0 2 10 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage v dd_otp t a = 25c 5.25 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current i dd_otp v dd_otp = 5.5 v, t a = 25c 100 ma power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 9 bandwidth C3 db bw_2.5k code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k?, r s = 0 3.2 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5172/ad5173 rev. b | page 4 of 24 electrical characteristics10 k?, 50 k?, 100 k? versions v dd = 5 v 10% or 3 v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c C20 +20 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C2.5 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage 8 v dd_otp 5.25 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 9 i dd_otp v dd_otp = 5.5 v, t a = 25c 100 ma power dissipation 10 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = +5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 11 bandwidth C3 db bw r ab = 10 k?, code = 0x80 600 khz r ab = 50 k?, code = 0x80 100 khz r ab = 100 k?, code = 0x80 40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 different from operating power supply, po wer supply otp is us ed one time only. 9 different from operating current, supply current fo r otp lasts approximately 400 ms for one time only. 10 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 11 all dynamic characteristics use v dd = 5 v.
ad5172/ad5173 rev. b | page 5 of 24 timing characteristics2.5 k?, 10 k?, 50 k?, 100 k? versions v dd = 5 v 10% or 3 v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 3. parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time 2 t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 see the timing diagrams (figure 51 to fi gure 55) for locations of measured values. 2 the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal.
ad5172/ad5173 r e v. b | pa ge 6 o f 2 4 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 4. p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v v a , v b , v w to gn d v dd terminal current, axCbx, axCwx, bxCwx 1 pulsed 2 0 m a c o n t i n u o u s 5 m a digital inputs and output vo ltage to gnd 0 v to 7 v operating tem p erature range C40c to +125c maximum junction temperature (t jmax ) 1 5 0 c storage temperature C65c to +150c lead temperature (soldering, 10 s) 300c t h ermal resista n ce 2 ja : msop-10 230c/w 1 maximum terminal current is bound b y the maximum cur r ent handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 pa cka g e pow e r di s s i p a t i o n = (t j max C t a )/ ja . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5172/ad5173 r e v. b | pa ge 7 o f 2 4 pin conf igura t ion and fu nction descriptions 10 9 8 7 1 2 3 4 b1 a1 w2 w1 b2 a2 sda gnd 6 5 scl v dd top view ad5172 04103-0-045 f i g u re 3. a d 51 72 p i n conf ig ur at io n 10 9 8 7 1 2 3 4 b1 ad0 w2 w1 b2 ad1 sda gnd 6 5 scl v dd top view ad5173 04103-0-046 f i g u re 4. a d 51 73 p i n conf ig ur at io n ta ble 5. a d 51 72 pi n f u nct i o n d e s c ri pt i o ns p i n m n e m o n i c d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a 1 a1 t e r m i n a l . 3 w 2 w2 t e r m i n a l . 4 g n d digital g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive-edg e triggered. 7 sda serial data inpu t/ output. 8 a 2 a2 t e r m i n a l . 9 b 2 b2 t e r m i n a l . 1 0 w 1 w1 t e r m i n a l . ta ble 6. a d 51 73 pi n f u nct i o n d e s c ri pt i o ns p i n m n e m o n i c d e s c r i p t i o n 1 b 1 b1 t e r m i n a l . 2 a d 0 programmab l e ad d r ess bit 0 for m u ltiple package decodi ng. 3 w 2 w2 t e r m i n a l . 4 g n d digital g r o u n d . 5 v dd positive power s u pply. 6 scl serial clock input. positive-edg e triggered. 7 sda serial data inpu t/ output. 8 a d 1 programmab l e ad d r ess bit 1 for m u ltiple package decodi ng. 9 b 2 b2 t e r m i n a l . 1 0 w 1 w1 t e r m i n a l .
ad5172/ad5173 r e v. b | pa ge 8 o f 2 4 typical perf orm ance cha r acte ristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-003 v dd = 5.5v t a = 25c r ab = 10k ? v dd = 2.7v f i gur e 5 . r - inl vs . co de vs . sup p l y v o l t a g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-004 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 6 . r - dnl vs . c o de vs . sup p l y v o lta g e s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-005 r ab = 10k ? v dd = 2.7v t a = ? 40c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 7 . inl vs . code vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-006 v dd = 2.7v; t a = ? 40 c, +25c, +85c, +125c r ab = 10k ? f i gur e 8 . dnl vs . c o de vs . t e m p e r a t ur e ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 p o te ntiome te r mode inl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-007 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 9 . inl vs . code vs . sup p l y v o l t age s ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 p o te ntiome te r mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-008 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v f i gur e 1 0 . dnl vs . c o de vs . sup p l y v o lta g e s
ad5172/ad5173 r e v. b | pa ge 9 o f 2 4 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-009 r ab = 10k ? v dd = 2.7v t a = ? 40 c, +25c, +85c, +125c v dd = 5.5v t a = ? 40c, +25c, +85 c, +125c f i gur e 1 1 . r - inl vs . c o de vs . t e m p e r a t ur e ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rhe os tat mode dnl (ls b ) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-010 v dd = 2.7v, 5.5v; t a = ? 40c, +25 c, +85c, +125c r ab = 10k ? f i gur e 1 2 . r - dnl vs . c o de vs . t e m p e r a t ur e ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, fu ll- sc a l e er r o r ( l sb ) 1.0 1.5 2.0 temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04103-0-011 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 13. f u ll- s c al e e rror v s . t e m p er a t ur e 0 0.75 1.50 2.25 3.00 3.75 4.50 zs e , ze ro-s cale e rror (ls b ) temperature ( c) ?40 ? 25 ? 1 0 5 20 35 50 65 80 95 110 125 04103-0-012 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v f i gure 14. zero -s c a le e r r o r v s . t e mpe r a t ur e i dd , s u p p l y curre nt ( a) 0.1 1 10 ? 4 0 ? 7 2 6 5 9 9 2 125 temperature ( c) 04103-0-013 v dd = 5v v dd = 3v f i gure 15. sup p l y current v s . t e mper at ur e ?2 0 0 20 40 60 80 100 120 rheostat mode te mp co (ppm/ c) 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-014 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85 c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40c to +125 c f i g u re 16. r h e o s t at m o de t e mpco ?r wb /?t v s . code
ad5172/ad5173 rev. b | page 10 of 24 ?30 ?20 ?10 0 10 20 p o te ntiome te r mode te mp co (ppm/ c) 30 40 50 12 8 96 32 64 0 1 60 192 224 256 code (decimal) 04103-0-047 r ab = 10k ? v dd = 2.7v t a = ? 40c to +85c, ? 40c to +125c v dd = 5.5v t a = ? 40c to +85c, ? 40 c to +125 c f i gur e 1 7 . ad51 72 p o t e nt i o m e t e r mode t e m p c o ? v wb /?t vs . c o de ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1m 100k 10m 04103-0-048 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 2. 5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-049 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 19. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-050 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 20. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 1k 100k 10k 1m 04103-0-051 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 f i gure 21. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain ( d b) frequency (hz) 10k 1k 100k 1m 10m 04103-0-052 100k ? 60khz 50k ? 120khz 10k ? 570khz 2.5k ? 2.2mhz f i gure 22. C3 db bandwidth @ code = 0x80
ad5172/ad5173 rev. b | page 11 of 24 i dd , s u p p ly curre nt (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04103-0-057 t a = 25c v dd = 2.7v v dd = 5.5v f i g u re 23. i dd vs . input v o l t a g e 04103-0-053 scl v w f i gure 2 4 . di g i ta l f eedthro u g h 04103-0-054 v w1 v w2 f i g u re 25. d i g i t a l c r os s t a l k 04103-0-056 v w1 v w2 f i g u re 26. a n a l og cr os s t alk 04103-0-058 v w f i g u re 27. m i ds c a l e gli t ch, cod e 0x 80 t o 0x 7f 04103-0-055 scl v w f i gure 2 8 . la r g e s i gna l s e ttli n g t i m e
ad5172/ad5173 rev. b | page 12 of 24 test circuits f i gur e 29 t o f i g u r e 36 il l u s t ra t e th e t e s t c i r c ui ts tha t def i ne t h e t e st con d i t io ns us e d i n t h e p r o d uc t sp e c if ic a t i o n t a b l es. 04103-0-015 v ms a w b dut v+ v + = v dd 1lsb = v + / 2 n f i gure 29. p o tenti o meter d i v i d e r n o n l ine a r i t y e r r o r (inl, dnl) 04103-0-016 no connect i w v ms a w b dut f i gur e 3 0 . resi st or p o si tio n no nl inea r i t y er r o r (r heo s ta t o p er a t ion; r - inl, r - dnl) 04103-0-017 v ms1 i w = v dd /r nominal v ms2 v w r w = [v ms1 ? v ms2 ]/ i w a w b dut f i gur e 3 1 . wi p e r resi sta n c e 04103-0-018 ? v ms % dd % pss (% / %) = v+ = v dd 10% psrr (db) = 20 log dut ms dd ( ) v dd v a v ms a w b v+ ? v ? v ? v f i g u re 32. p o wer s u p p ly s e ns it iv it y ( p ss, pssr ) 04103-0-019 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in f i gure 33. t e s t c i rc uit for g a in v s . f r eq uenc y 04103-0-020 w b dut i sw code = 0x00 r sw = 0.1v i sw 0.1v gnd to v dd f i gu r e 3 4 . i n cr em en ta l on re si sta n c e 04103-0-021 v dd a w b dut gnd i cm v cm nc nc f i g u re 35. co m m o n -m ode l e ak ag e current 04103-0-022 v in n/c w1 b1 b2 w2 rdac1 a1 rdac2 v dd v ss v out cta = 20 log[v out /v in ] a2 f i g u re 36. a n a l og cr os s t alk
ad5172/ad5173 rev. b | page 13 of 24 theor y of opera tion the ad5172 /ad5173 a r e 256-p o si tio n , dig i tal l y co n t r o l l ed va r i ab le r e sis t o r s (vrs) tha t e m p l o y f u s e link t e c h n o log y t o a c h i e v e me mor y re te n t i o n of re s i st anc e s e tt i n g . an in t e r n al p o w e r - o n p r es e t places t h e w i p e r a t mids c a le d u r i ng p o we r - o n . i f t h e ot p f u nc t i o n h a s b e e n a c t i v a te d , t h e de vi ce p o w e rs u p a t t h e us er -def i n e d p e r m an e n t s e t t ing. one- time progr a mming ( o tp) p r io r t o o t p ac ti va t i o n , t h e ad5172/ad5173 p r es ets t o mid- s c a l e d u r i ng in i t ia l p o w e r - on. a f t e r t h e w i p e r is s e t t o t h e desir e d p o si t i o n , th e r e sis t ance ca n be p e r m an e n tl y s e t b y p r og ra mmin g t h e t b i t hig h , t h e p r o p er co di n g (s e e t a b l e 7 and ta b l e 8 ) , a n d o n e - t i m e v dd _ o t p . the f u s e link t e c h n o log y o f th e ad517x fa mil y o f dig i t a l p o t e n t io m e t e rs r e q u ires v dd _ o tp to b e betw een 5.25 v a nd 5.5 v t o b l o w t h e f u s e s t o ac hiev e a g i v e n n o n v o l a t ile s e t t in g. c o n v e r se l y , v dd ca n be 2.7 v t o 5.5 v d u r i ng op e r a t ion. a s a re su l t , s y ste m su p p ly t h a t is l o we r t h an 5.25 v r e q u ir es a n ext e r n al su p p l y f o r o n e-time p r og ra mmin g . the us er is al lo w e d o n l y o n e a t t e m p t t o b l o w t h e f u s e s. i f t h e a t t e m p t, t h e f u s e s s t r u c t ur es ma y c h a n g e s u ch tha t t h ey mig h t ne v e r b e b l o w n, r e ga r d les s o f t h e en erg y a p plie d a t s u b s e q ue n t ev en ts . f o r d e ta i l s , se e t h e p o w e r s u p p l y c o n s id era t i o n s s e ct i o n. the d e v i ce con t r o l cir c ui t has t w o va li da t i o n b i ts, e1 a nd e0, tha t c a n be r e ad bac k t o ch ec k t h e p r og ra mming s t a t us (s ee t a b l e 9). u s ers sh o u ld al wa ys r e ad back t h e valida tio n b i ts t o en s u r e t h a t t h e f u s e s a r e p r o p erl y b l o w n. af t e r t h e f u s e s ha v e be e n b l o w n, al l f u s e la t c h e s a r e ena b le d u p o n su bs e q u e n t p o w e r - on; t h er e f o r e , t h e o u t p u t co r r es p o n d s t o t h e s t o r e d s e t t ing. f i gur e 3 8 s h o w s a detailed f u nc tio n al b l o c k dia g ra m. progr a mm ing the v a riable resi st or and v o l t a g e r h eos t at ope r ation the n o minal r e sis t a n c e o f the rd a c be tw e e n t e r m inals a and b is a v a i la b l e in 2.5 k?, 10 k?, 50 k?, a nd 100 k?. th e n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s ed b y t h e w i p e r t e r m i n al , an d t h e b t e r m inal co n t ac t. the 8- b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f t h e 256 p o s s i b l e se t t i n g s . a w b a w b a w b 04103-0-027 f i g u re 37. r h e o s t at m o de conf ig ur at i o n a s sumi n g a 10 k? p a r t is us e d , t h e w i p e r s f i rst co nn e c t i o n s t a r ts a t t h e b t e r m inal fo r da t a 0x00. b e ca us e t h er e is a 50 ? wi p e r co n t ac t r e sis t a n c e , s u ch a co nn ec t i o n y i e l ds a minim u m o f 100 ? (2 5 0 ?) r e sis t a n ce betw een t e r m inals w an d b . the s e c o n d c o n n e c ti o n i s th e fi r s t ta p po i n t , w h i c h co rr e s po n d s t o 139 ? (r wb = r ab /2 56 + 2 r w = 39 ? + 2 50 ?) f o r da ta 0x0 1 . the thir d co nn e c tio n is t h e n e xt ta p p o in t, r e p r es en t i n g 178 ? (2 39 ? + 2 50 ?) f o r da t a 0 x 02, a n d s o o n . e a c h ls b da ta val u e i n cr e a s e m o v e s t h e wi p e r u p t h e r e sis t o r ladder un t i l t h e las t t a p p o in t is r e ac h e d a t 10,10 0 ? (r ab + 2 r w ). sda scl a w b fuses en dac reg. i 2 c interface comparator one-time program/test control block mux decoder fuse reg. 04103-0-026 f i g u re 38. d e t a iled f u nc t i on al bl ock d i ag r a m
ad5172/ad5173 rev. b | page 14 of 24 d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 04103-0-028 f i gur e 3 9 . ad51 72 /ad5 17 3 e q ui v a l e nt rd a c cir c ui t the g e n e ral e q u a t i o n t h a t det e r m i n es t h e dig i t a l l y p r ogra mm e d o u t p ut r e sist a n c e b e tw e e n w and b is w ab wb r r d d r + = 2 128 ) ( ( 1 ) w h er e d is t h e de cima l e q ui v a l e n t o f t h e b i na r y co de lo ade d i n t h e 8 - b i t r d a c r e g i s t er , r ab is t h e e nd- to -e n d resist a n c e , an d r w is th e wi p e r r e sis t a n ce con t r i b u t e d b y the o n r e sis t an ce o f th e i n t e rn al sw i t c h . i n su mma r y , if r ab = 10 k? and t h e a t e r m i n a l is op e n -c ir c u i t e d , th e o u t p u t r e si s t a n ce r wb is s e t fo r t h e r d a c la tch co des, as shown i n t a bl e 7 . ta ble 7. co des a nd corr es po n d i n g r wb resist an ce d (dec.) r wb (?) output state 2 5 5 9 , 9 6 1 full-scale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 1 3 9 1 l s b 0 100 zero-scale (wiper contact resistance) n o t e th a t i n th e z e r o - s ca l e c o n d i t i o n , a fi n i t e w i pe r r e s i s t a n ce o f 100 ? is p r es en t. ca r e sh o u ld b e tak e n t o limi t t h e c u r r en t f l o w b e tw e e n w an d b in t h is s t a t e to a maxim u m pu ls e c u r r en t o f n o m o r e tha n 2 0 ma. o t h e r w is e , deg r ada t io n or p o s s i b le dest r u c t io n o f t h e in ter n a l s w i t ch co n t ac t can o c c u r . simi la r to t h e me cha n ic a l p o te n t io meter , t h e r e s i st an ce o f t h e rd a c bet w een th e wi per w a n d t e rm in al a also p r od uces a d i gi tall y c o n t r o ll ed c o m p l e m e n t a r y r e s i s t a n c e , r wa . w h e n t h es e t e r m inals a r e us e d , t h e b t e r m inal ca n b e op e n e d . s e t t i n g t h e re s i st anc e v a lu e f o r r wa st ar ts a t a max i m u m v a lu e of re s i st anc e a nd de cr e a s e s a s t h e d a t a lo ade d i n t h e l a tch i n cr e a s e s in va l u e. the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r + = 2 128 C 256 ) ( ( 2 ) fo r r ab = 10 k ? a n d t h e b t e rmin al o p en -ci r cui t ed , t h e fol l o w ing ou tp u t re s i st anc e r wa is s e t f o r th e rd a c la t c h co des, as sho w n in t a ble 8. ta ble 8. co des a nd corr es po n d i n g r wa resist an ce d (dec) r wa (?) output state 2 5 5 1 3 9 f u l l - s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o - s c a l e t y p i ca l d e vice -to - de vic e ma tchi n g is p r o c ess-lot dep e nde n t a nd ma y va r y b y u p t o 30%. b e ca us e t h e r e sis t a n ce e l e m e n t i s p r oce s sed usin g th in f i lm t e ch n o log y , t h e c h a n g e in r ab wi t h t e m p era t ur e has a v e r y lo w 35 p p m / c t e m p er a t ur e co ef f i cien t. progr a mm ing the po tent iome t e r divi der voltage o u tp ut ope r ation t h e digi t a l p o t e n t io m e ter easil y g e n e ra t e s a v o l t a g e di vid e r a t w i p e r - to - b a n d w i p e r - to - a prop or t i ona l to t h e i n put volt age a t a - t o -b . u n lik e t h e p o la r i ty o f v dd to g n d , w h i c h m u st b e p o s i - t i v e , v o l t a g e acr o s s a - b , w - a, and w - b can b e a t ei t h er p o la r i t y . a v i w b v o 04103-0-029 f i gure 40. p o tentiometer m o de c o nf ig ur ation i f ig n o r i n g t h e e f fe c t o f t h e w i p e r r e sist a n ce fo r a p p r o x im a t io n, c o nne c t i ng t h e a te r m i n a l to 5 v and t h e b te r m i n a l to g r ou nd p r o d uces a n o u t p u t v o l t a g e a t t h e wi p e r - t o -b star tin g a t 0 v u p t o 1 l s b less t h an 5 v . e a ch l s b o f v o l t a g e i s e q u a l t o t h e v o l t age a p p l ie d acr o s s ter m inal ab divided b y t h e 256 p o si tio n s o f t h e p o ten t iom e ter d i vi der . t h e ge n e r a l e q ua t i o n def i ning t h e o u t p u t vol t age a t v w w i t h r e sp e c t to g r o u nd fo r a n y va lid i n p u t vol t a g e a p plie d to ter m i n a l s a a nd b is b a w v d v d d v 256 256 256 ) ( ? + = ( 3 ) f o r a m o r e acc u ra t e c a lc u l a t io n, w h ich in cl udes t h e ef fe c t o f wi p e r r e sist an ce, v w ca n b e fo u nd as b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = ( 4 ) ope r a t i o n o f th e d i g i tal po t e n t io m e t e r i n th e di v i de r m o d e re su lt s i n a more a c c u r a t e op e r at i o n o v e r te m p e r a t u r e. u n l i ke t h e rh e o st a t mo de , t h e o u t p ut vol t a g e is dep e n d en t mainl y o n th e ra ti o o f th e in t e rn al r e si s t o r s r wa a nd r wb and n o t t h e abs o - l u t e va l u es. th us, t h e t e m p era t u r e dr if t r e d u ces t o 15 p p m / c.
ad5172/ad5173 rev. b | page 15 of 24 esd pro t ec tion al l d i g i t a l i n p u t s s d a , s c l, a d 0, a nd a d 1 a r e p r o t e c te d wi th a ser i es in p u t r e sis t o r a n d p a ralle l z e n e r e s d s t r u ct ur es, as sho w n i n f i gur e 41 a nd f i gur e 4 2 . logic 340 ? gnd 04103-0-030 f i g u re 41. e s d pr ot ec t i o n of d i g i t a l p i ns a,b,w gnd 04103-0-031 f i g u re 42. e s d pr ot ec t i o n of r e s i s t o r t e r m in als terminal vol t a g e o p e r a t ing r a nge the ad5172 /ad5173 v dd to g n d p o we r su p p ly de f i ne s t h e b o u nda r y co ndi t i o n s fo r p r o p er 3-ter m in a l d i g i t a l p o te n t io- m e t e r o p era t io n. s u p pl y sig n als p r es en t o n t e r m inals a, b , and w t h a t exce e d v dd o r gnd a r e c l am p e d b y t h e in t e r n al f o r w a r d- b i as e d dio d es (s ee f i gur e 43). gnd a w b v dd 04103-0-032 f i g u re 43. m a x i mu m t e r m i n a l v o lt ag es s e t by v dd and g nd power-up sequence b e ca us e t h e esd p r o t e c t i o n di o d es limi t t h e vol t a g e co m p l i ance a t ter m in a ls a , b , and w ( s e e f i gur e 43), i t is i m p o r t a n t to p o w e r v dd /gnd bef o r e a p p l yin g a n y v o l t a g e t o t e r m i n als a, b , a n d w . ot h e r w ise , t h e di o d e i s f o r w a r d b i a s e d s u ch tha t v d d is po w e r e d unin t e n t io nal l y a nd ma y a f fe c t t h e r e s t o f t h e us er s cir c ui t . th e i d eal po w e r - u p seq u en ce i s gnd , v d d , t h e digi tal in p u t s , a n d t h e n v a /vb/v w . the r e l a t i ve o r der o f p o w e r i n g v a , vb , v w , a nd t h e dig i t a l i n p u ts is n o t i m p o r t a n t as lo n g as t h e y a r e po w e r e d a f t e r vd d / gn d . po wer sup p l y c o nsi d er a t ions t o m i n i m i z e th e pa c k a g e p i n co u n t , b o th th e o n e - t i m e p r o - g r a mmin g and n o r m al o p er a t in g v o l t a g e s u p p l i es a r e a p plie d to th e s a m e v dd t e r m inal o f t h e de vic e . th e ad51 72/ ad5173 em p l o y f u s e lin k t e c h n o log y tha t r e q u ir es 5.25 v t o 5.5v t o bl o w t h e i n te r n a l f u s e s to a c h i e v e a g i ve n s e t t i n g , b u t nor m a l v dd ca n be 2.7 v t o 5.5v . s u c h d u al-v ol t a g e r e q u ir em en ts r e q u ir e is ola t ion b e t w e e n t h e su p p lies if v dd is lo w e r tha n t h e re qu i r e d v dd _ o tp . t h e f u s e pro g r a m m i ng s u pp l y ( e it he r a n on - bo a r d r e gula t o r o r rac k -m o u n t p o w e r s u p p l y ) m u s t be ra ted a t 5.25 v t o 5.5 v a nd m u s t b e a b l e t o p r o v ide a 1 00 ma tra n sien t c u r r en t f o r 400 m s f o r s u cces sf u l o n e-t i m e p r og ra mming. o n c e t h e p e r m an e n t s e t t in g p r og ra m m in g is com p lete , t h e v dd _ o t p su p p ly m u st b e re mo ve d. t h e d e v i c e t h e n op e r a t e s a t v dd and c o nsu m e s on ly m i c r o a m p s of c u r r e n t . f i g u re 4 4 sh o w s t h e s i m p l e s t i m p l em en ta ti o n t o m e e t t h e d u al v o l t a g e r e q u i r em en t wi t h a j u m p er . this a p p r o a ch s a v e s on e v o l t a g e s u p p l y , b u t dr a w s ad di t i o n a l c u r r en t an d r e q u ir es ma n u a l c o nf igur a t io n. v dd 5.5v r1 50k ? r2 c1 10 f c2 1nf 250k ? 5v connect j1 here for otp connect j1 here after otp ad5172/ ad5173 04103-0-033 f i g u re 44. p o wer s u p p ly r e qu ire m ent an al t e r n a t e a p p r o a c h in 3.5 v t o 5.25 v sys t em s adds a sig n a l dio d e b e twe e n t h e s y ste m sup p ly and t h e o t p s u p p ly for is ola t ion, as sh o w n i n f i gur e 45 . v dd 3.5v? 5.2v 5.5v d1 c1 10 f c2 1nf apply for otp only ad5172/ ad5173 04103-0-034 f i g u re 45. is ol at e 5. 5 v o t p s u p p ly f r o m 3.5 v to 5. 2 5 v n o r m a l o p e r at ing sup p ly . th e v dd_o t p s u p p ly m u s t be r e mo ved on c e o t p is c o mple ted .
ad5172/ad5173 rev. b | page 16 of 24 v dd 2.7v 5.5v p1 p1 = p2 = fdv302p, nds0610 r1 10k ? p2 c1 10 f c2 1nf apply for otp onl y ad5172/ ad5173 04103-0-035 f i g u re 46. is ol at e 5. 5 v o t p s u p p ly f r o m 2.7 v n o r m a l o p er at ing su p p ly . the v dd_o t p m u s t b e rem o ved once o t p is c o mpl e ted. f o r us ers w h o o p era t e t h eir sys t em s a t 2.7 v , us e o f t h e b i dir e c - t i o n a l lo w t h r e sh old p - c h mosf et s is r e co m m ende d fo r t h e su p p ly s is ol a t ion. a s s h ow n i n f i g u re 4 6 , t h is a ssu me s t h a t t h e 2.7 v sy stem vo l t a g e is a p plie d f i rst, and t h a t t h e p1 a nd p2 g a te s are pu l l e d to g r ou nd, t h u s t u r n i n g on p 1 a nd su b s e q u e n t l y p2. a s a r e s u l t , v dd o f th e ad5 172/ad5173 a p p r o a c h es 2.7 v . w h en t h e ad5 172/ad5173 s e t t in g is f o und , t h e fac t o r y t e s t er ap p l i e s t h e v dd _ot p t o b o th th e v dd a nd t h e mos f et s ga t e s t h us t u r n in g p1 an d p2 o f f . th e otp co mman d sho u ld be exe c u t e d a t this t i m e t o p r og ra m th e ad5172/ad5173 while t h e 2.7 v s o ur ce is p r o t ec t e d . o n c e t h e otp is co m p let e d, th e t e s t er w i th d r a w s th e v dd _ o tp a nd t h e ad5172/ad51 73 s s e t t in g is fi x e d p e r m a n e n t l y . the ad5172 /ad5173 ac hiev e t h e otp f u n c tion b y b l o w in g in t e r n al f u s e s. u s ers sh o u ld alwa ys a p p l y t h e 5.25 v t o 5.5 v o n e- t i m e p r og ra m v o l t a g e r e q u ir em e n t a t t h e f i rs t f u s e p r o- g r a mmin g a t t e m p t. f a i l ur e t o co m p l y w i t h t h i s r e q u ir emen t ma y lead t o the c h a n g e o f f u s e str u c t ur es, r e n d er in g p r o g ra mmin g i n o p erab le. p o o r pc b la y o u t i n tr o d uce s pa ra si ti cs tha t ca n a f f e ct fuse p r o g ra mmin g . ther efo r e, i t is r e co mme n d e d to add a 1 f to 10 f t a n t al u m c a p a ci t o r in p a r a l l e l wi t h a 1 nf ceramic c a p a c i to r as clos e as p o ssib le t o t h e v dd p i n. t h e ty p e and va l u e ch o s e n f o r b o t h ca p a ci t o r s a r e im po r t a n t . th is co m b ina t i o n o f ca pa ci t o r v a l u e s p r o v ide s b o t h a f a st re sp ons e and l a rge r su p p ly c u r r e n t ha nd lin g w i t h mini m u m sup p ly dr o o p d u r i n g t r a n sien ts . a s a r e s u l t , t h es e ca p a ci t o rs i n cr e a s e t h e o t p p r og ra mming s u cces s b y n o t i n hi b i t i ng t h e p r op er energ y n e e d e d t o b l o w t h e in t e r n al fu se s . a d di ti o n all y , c 1 minimizes tra n sie n t dist urban c e and lo w f r e q u e nc y r i ppl e , w h i l e c 2 re du c e s h i g h f r e q u e nc y noi s e d u r i ng nor m a l op e r a t i o n . l a y o ut c o nsider a t i o ns i n pc b l a yo u t , i t is a g o o d p r ac t i ce t o em p l o y c o m p ac t, minim u m le ad-len gth des i g n . th e le ads t o t h e in p u ts sh o u ld be as dir e c t as p o ssi b le w i t h a m i ni m u m cond uc tor len g t h . gr o u nd p a th s sh o u l d ha v e lo w r e sis t an c e a nd lo w in d u c t a n c e . n o te t h a t t h e d i g i t a l g r ou nd sh ou l d a l s o b e j o i n e d re motely to t h e analog g r o u nd a t on e p o in t t o minimi ze t h e g r o u n d b o u n ce. v dd gnd v dd c1 10 f c2 1nf ad5172 + 04103-0-036 f i g u r e 4 7 . p o w e r su pp l y by pa s s i n g
ad5172/ad5173 rev. b | page 17 of 24 ev alua tion softw a re/hardw are f i gur e 4 8 . ad51 72 /ad5 17 3 c o m p ute r so f t w a r e int e r f a c e ther e a r e tw o wa ys o f co n t r o l l in g th e ad5172 /ad5173. u s ers ca n ei t h er p r og ra m t h e de vices wi th com p u t er s o f t wa r e o r wi t h ext e r n al i 2 c co n t r o l l ers. soft w a re progr a mm ing t a k i n g ad van t age o f t h e on e - t i m e p r og ra mmi n g fe a t ur e, us ers ma y co n s ider p r og ra mmin g t h e de vice in t h e fac t o r y b e fo r e s h i p p i n g i t t o end u s e rs. ad i o f f e rs a de vice p r og ra mmin g s o f t wa r e t h a t can b e im p l em en ted as a n exec u t ab le o n pcs r u n n i ng w i nd ow s 9 5 or l a te r . as a re su lt , e x te r n a l c o n t ro l l e r s a r e n o t r e q u ir e d , w h ich sig n if i c a n t l y r e d u ces d e v e l o p m e n t t i me. the p r o g r a m is e a sy to us e a nd s e t u p , an d us er s do n o t n e e d to ha v e p r og ra mmin g s k il ls. f i gure 48 sh o w s t h e us er in t e r f ac e . the s o f t wa r e can b e do w n lo ade d f r o m w w w . a n a l o g .co m . b e f o r e o n e-t i me p r og ra mmin g is s e t, t h e ad51 72/ad5173 sta r t a t mids c a le a f t e r p o w e r - u p . t o i n cr e m en t o r de cr em e n t t h e r e sis t a n ce, t h e us er ma y si m p l y m o ve t h e s c r o l l b a rs o n t h e lef t . t o wr i t e an y s p e c if ic val u e , t h e us er s h o u l d us e t h e b i t p a t t er n in t h e u p p e r s c r e e n an d click r u n . the fo r m a t o f wr i t in g d a t a t o t h e de vi ce is sho w n i n t a b l e 9. on ce t h e desir e d s e t t i n g is s e le c t e d , cl ick pr og ra m p e r m a n en t t o b l o w t h e i n t e r n al f u s e links. t o re a d t h e v a l i d a t i on bit s a n d d a t a out f r om t h e d e v i c e , cl i c k re ad . the fo r m a t o f t h e r e ad b i ts is sh o w n in t a b l e 10. t o a p pl y t h e de vice p r og ra mmin g s o f t wa r e i n t h e f a c t o r y , us ers m u s t m o dif y a p a ral l e l p o r t cab l e a nd co nf igu r e p i n s 2, 3, 15, and 2 5 fo r s d a _ wr i t e , s c l , s d a_re ad, and d g nd , r e sp e c t i ve ly , fo r th e co n t r o l sig n als (f igur e 4 9 ). u s ers sh o u ld als o la y o u t t h e pcb o f the ad5 172/ad5173 wi th scl and s d a p a ds, as sh o w n in f i gur e 50, s u c h tha t p o g o p i n s can b e ins e r t ed f o r fac t o r y p r o g ra mmin g .
ad5172/ad5173 rev. b | page 18 of 24 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100 ? r2 100 ? r1 100 ? sda read write 04103-0-037 f i g u re 49. p a r a l l e l p o r t con n ec t i on. p i n 2 = sda _ w r it e , p i n 3 = scl, p i n 15 = s d a _ r e ad , and pin 2 5 = dgn d . ad5172 ad5173 w1 b2 a2 sda scl b1 ad0 w2 gnd v dd b1 a1 w2 gnd v dd w1 b2 ad1 sda scl 04103-0-038 f i gur e 5 0 . re c o mme nde d ad5 172 / a d5 17 3 p c b la yo ut. the scl a n d sd a pads allo w pog o pins t o b e inser t ed s o t h at s i g n als c a n be c o m m un ic ated thr o u g h the par a l l el por t fo r prog r a m m ing ( f ig u r e 4 9 ) .
ad5172/ad5173 rev. b | page 19 of 24 i 2 c interface table 9. write mode ad5172 s 0 1 0 1 1 1 1 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte ad5173 s 0 1 0 1 1 ad1 ad0 w a a0 sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 10. read mode ad5172 s 0 1 0 1 1 1 1 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte ad5173 s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte instruction byte data byte the following is the legend for table 9 and table 10. s = start condition p = stop condition a = acknowledge ad0, ad1 = package pin programmable address bits x = dont care w = write r = read a0 = rdac subaddress select bit sd = shutdown connects wiper to b terminal and open circuits the a terminal. it does not change contents of wiper register. t = otp programming bit. logic 1 programs the wiper permanently. ow = overwrite the fuse setting and program the digital potentiometer to a different setting. note that upon power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on whether not the fuse link has been blown. d7, d6, d5, d4, d3, d2, d1, d0 = data bits. e1, e0 = otp validation bits. 0, 0 = ready to program. 1, 0 = fatal error. some fuses not blown. do not retry. discard this unit. 1, 1 = programmed successfully. no further adjustments possible.
ad5172/ad5173 rev. b | page 20 of 24 04103-0-039 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p f i g u r e 51. i 2 c inter f a c e d e ta il ed ti mi ng di a g r a m 04103-0-040 scl start by master sda 01 1 frame 1 slave address byte 0 1111 frame 2 instruction byte ack by ad5172 r/w a0 sd 0 o w x x x 1 9 d7 d6 d5 d4 d3 ack by ad5172 frame 3 data byte 1 9 t stop by master 9 d2 d1 d0 ack by ad5172 f i g u r e 52. w r it ing t o t h e r d a c r e g i s t e r a d5 17 2 04103-0-041 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w a0 sd 0 o w x x x 1 9 d7 d6 d5 d4 d3 ack by ad5173 frame 3 data byte 1 9 t stop by master 9 d2 d1 d0 ack by ad5173 f i g u re 53. w r it ing t o t h e r d a c r e g i s t e r a d5 17 3 04103-0-042 scl start by master sda 01 1 frame 1 slave address byte 0 111 1 frame 2 instruction byte ack by ad5172 r/w d7 d6 d4 d3 d2 d1 d0 1 9 e1 e0 x x x ack by master frame 3 data byte 1 9 d5 stop by master 9 xx x no ack by master f i g u re 54. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 17 2 04103-0-043 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5173 r/w d7 d6 d4 d3 d2 d1 d0 1 9 e1 e0 x x x ack by master frame 3 data byte 1 9 d5 stop by master 9 xx x no ack by master f i g u re 55. r e ad ing d a t a f r o m a p r ev i o us ly s e lec t ed r d a c r e g i s t er in writ e m o de a d5 17 3
ad5172/ad5173 rev. b | page 21 of 24 i 2 c-compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 52 and figure 53). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5172 has a fixed slave address byte, whereas the ad5173 has two configurable address bits, ad0 and ad1 (see figure 52 and figure 53). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. in write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is the rdac subaddress select bit. a logic low selects channel 1; a logic high selects channel 2. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. also, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the third msb, t, is the otp programming bit. a logic high blows the internal fuses and programs the resistor setting permanently. the fourth msb must always be at logic 0. the fifth msb, ow, is an overwrite bit. when raised to a logic high, ow allows the rdac setting to be changed even after the internal fuses have been blown. however, once ow is returned to a logic 0, the position of the rdac returns to the setting prior to overwrite. because ow is not static, if the device is powered off and on, the rdac presets to midscale or to the setting at which the fuses were blown, depending on whether or not the fuses have been permanently set already. the remainder of the bits in the instruction byte are dont cares (see figure 52 and figure 53). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 51). in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from write mode, where there are eight data bits followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 54 and figure 55). the channel of interest is the one that is previously selected in the write mode. when users need to read the rdac values of both channels, they must program the first channel in write mode and then change to read mode to read the first channel value. after that, the user must change back to write mode with the second channel selected and read the second channel value in read mode. it is not necessary for users to issue the frame 3 data byte in write mode for subsequent readback operation. refer to figure 54 and figure 55 for the programming format. following the data byte, the validation byte contains two validation bits, e0 and e1. these bits signify the status of the one-time programming (see figure 54 and figure 55). after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low- to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 52 and figure 53). in read mode, the master issues a no acknowledge for the ninth clock pulse, i.e., the sda line remains high. the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 54 and figure 55). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowl- edged its slave address and instruction bytes in write mode, the rdac output is updated on each successive byte. if different instructions are needed, write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5172/ad5173 rev. b | page 22 of 24 table 11. validation status e 1 e 0 s t a t u s 0 0 r e a d y for p r o g r a m m i n g . 1 0 fatal error. som e fuses not blown. do not retry. discard this unit. 1 1 successful. no further programming i s possi ble. multiple dev i ces on one bus (ad5173 only) i gur e 5 sh o s o ur ad5173s o n t h e s a e s e r i al u s a c h has a i er en t s l a v e ar es s e ca us e t h e s t a t es o t h eir ad an ad1 p i n s a r e i er en t his al l o s e a ch e v i ce o n t h e u s t o e r i t te n to o r r e a r o i n e p e ne n t ly h e aster e v i ce output u s l i n e r ive r s are op e n r a i n pu l l o ns i n a u l l y co p a t i le in t e r ace sda sda ad1 ad0 master scl scl ad5173 sda ad1 ad0 scl ad5173 sda ad1 ad0 scl ad5173 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5173 04103-0-044 f i g u re 56. m u lt ip le a d 51 73s on o n e i 2 c bus
ad5172/ad5173 rev. b | page 23 of 24 outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba f i gure 57. 1 0 -l ead m i ni s m al l o u tl ine p a ck ag e [msop ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s
ad5172/ad5173 rev. b | page 24 of 24 orderi ng guide m o d e l r ab (k?) temperature r a nge package descri ption package option branding ad5172brm2.5 2.5 C40c to +125c msop-10 rm-10 d0u ad5172brm2.5- rl7 2.5 C40c to +125c msop-10 rm-10 d0u ad5172brm10 10 C40c to +125c msop-10 rm-10 d0v ad5172brm10- rl7 10 C40c to +125c msop-10 rm-10 d0v ad5172brm50 50 C40c to +125c msop-10 rm-10 d10 ad5172brm50- rl7 50 C40c to +125c msop-10 rm-10 d10 AD5172BRMZ50 1 50 C40c to +125c msop-10 rm-10 d10 AD5172BRMZ50 -rl7 1 50 C40c to +125c msop-10 rm-10 d10 ad5172brm100 100 C40c to +125c msop-10 rm-10 d11 ad5172brm100 -rl7 100 C40c to +125c msop-10 rm-10 d11 ad5172eval 2 e v a l u a t i o n bo ar d ad5173brm2.5 2.5 C40c to +125c msop-10 rm-10 d1k ad5173brm2.5- rl7 2.5 C40c to +125c msop-10 rm-10 d1k ad5173brm10 10 C40c to +125c msop-10 rm-10 d1l ad5173brm10- rl7 10 C40c to +125c msop-10 rm-10 d1l ad5173brm50 50 C40c to +125c msop-10 rm-10 d1m ad5173brm50- rl7 50 C40c to +125c msop-10 rm-10 d1m ad5173brm100 100 C40c to +125c msop-10 rm-10 d1n ad5173brm100 -rl7 100 C40c to +125c msop-10 rm-10 d1n ad5173eval 2 e v a l u a t i o n bo ar d 1 z = pb-free part. 2 th e eval uat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s. p u rchase of l i c e nse d i 2 c c o m p onents of ana l og devi c e s or one of it s su bli c ense d a s so ciated comp anies con v eys a li c e nse for th e pu rc haser u n der th e p h i li p s i 2 c p a t e nt r i ghts t o u s e these c o mponents in an i 2 c sy st em, pro v ided that the sy st em confor ms to the i 2 c standa r d s p e c ificati o n as defin e d by p h ili p s . ? 2004 a n al og devic e s , inc . a ll righ ts r e ser v e d . t r a d em arks an d r e gist er e d tr ade m ar ks ar e the pr oper t y of their r e spec tiv e o w ne rs . c04103C0 C 11/04(b)

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